With the progress of microtechnology in the semiconductor manufacturing field, the physical dimensions of semiconductor devices are becoming increasingly smaller. As these devices become smaller, the contact area has been reduced to dimensions below 1 .mu.m. However, due to the reduction of the contact area, contact resistance increases. Further, a step coverage defect may occur at the stepped portion due to a high aspect ratio, which is caused by microscale processing.
Meanwhile, since dynamic DRAM semiconductor devices are being manufactured in densities of mega-bit order, various capacitor structures have been proposed to obtain sufficient capacitances in a limited space. Particularly, in the semiconductor devices of a 4Mbit scale, a stacked capacitor (STC) structure is generally used because it is simple to manufacture and it has a high immunity against soft errors.
The conventional STC has a capacitor structure stacked on an access transistor which is formed on a semiconductor substrate. The capacitor consists of a storage node (i.e., a lower electrode), a dielectric film and an upper electrode. The storage node contacts the source (diffused or ion-implanted region) of the access transistor and usually is formed of polycrystalline silicon doped with an impurity.
However, the conventional STC has several drawbacks. First, the defects of the polycrystalline silicon are distributed over the source (doped region), which cause current leaks at the contact portion. Accordingly, the reliability of the semiconductor device is reduced. Further, the conventional STC has a structural characteristic wherein its capacitance decreases as its density increases. As a result, 4Mbit devices form a limit in conventional semiconductor manufacturing techniques.
Therefore, to manufacture a 16Mbit or a 64Mbit device, the limited space must be utilized more effectively. Accordingly, multi-layer structures, built in the upward direction above the substrate, or in the downward direction in a trench etched in the substrate, have been proposed to increase the effective total area of the capacitor. However, in the case where a multi-layer structure is formed in the upward direction, the contact hole of the drain (doped region) of the access transistor is deepened, thereby making it difficult to contact a bit line to the drain (diffused or ion-implanted region).